]> PCF29F64 8 K × 8-bit static CMOS EEPROM with PAGE-ERASE option January 1993 Philips 23433 VSS Negative supply voltage 0 V Tamb Ambient temperature range -40 to +85 °C VCE CE Chip enable input (voltage) VIL V VCE CE Chip enable input (voltage) VIH V VOE OE Output enable input (voltage) VIL V VWE WE Write enable input (voltage) VIH V f frequency 5 M Hz all other pins VIL or VIH V IOH High-level output current -400 µ A IOL Low-level output current 2.1 m A VO Output voltage VDD or VSS V VI Input voltage VDD or VSS V VI/O Input/output voltage VSS V |ZI| Input impedance > 500 Ω VDD Supply voltage 5±10% V VDD Supply voltage 4.5 to 5.5 V Input pulse levels 0 to 3 V Input rise and fall times 10 n s Input and output timing levels 1.5 V Output load outputs open Output load 1 TTL gate and CL = 100 pF other inputs VIL or VIH V Input level CMOS input level Input level TTL input level VI Input voltage VSS V VDD Supply voltage range 4.5 V 5.5 V IDDR supply current READ 5.0 m A IDDW supply current ERASE/WRITE 10.0 m A IDDO supply current STANDBY 200 µ A IDDO supply current STANDBY 2 m A VIL LOW level input voltage (CMOS input level) VSS-0.3 V VSS+0.3 V VIL LOW level input voltage (TTL input level) -1.0 V 0.8 V VIH HIGH level input voltage (CMOS input level) VDD-0.3 V VDD+0.3 V VIH HIGH level input voltage (TTL input level) 2.0 V VDD+1.0 V VOL LOW level output voltage 0.4 V VOH HIGH level output voltage 2.4 V ILI Input leakage current 1 µ A ILO Output leakage current 1 µ A CI Input capacitance tbf p F CI/O input/output capacitance tbf p F tPU power-up to operation time 5 m s VDD supply voltage -0.3 V +7.0 V VI voltage on any input pin VSS-0.8 V VDD+0.8 V II current on any input pin 1 m A IO output current 5 m A Tstg storage temperature -65 °C +150 °C Tamb operating ambient temperature -40 °C +85 °C tRC read cycle time 200 n s tAA address access time 200 n s tCE chip enable access time 200 n s tOE output enable access time 100 n s tLZ chip enable to output LOW Z 0 n s tOHZ output disable to output HIGH Z 0 n s 50 n s tOLZ output enable to output LOW Z 0 n s tHZ chip disable to output HIGH Z 0 n s 50 n s tOH output hold time from address change 10 n s tAS address set-up time 10 n s tAH address hold time 200 n s tEC erase cycle time 4 m s 6 m s tWC write cycle time 2 m s 2.5 m s 3 m s tCS operation set-up time 0 n s tCH operation hold time 0 n s tCW chip enable pulse width 150 n s tOES output enable HIGH set-up time 10 n s tOEH output enable HIGH hold time 10 n s tWP write enable pulse width 150 n s tWPH write enable HIGH recovery time 50 n s tDV data valid time 300 n s tDS data set-up time 100 n s tDH data hold time 20 n s A0 A0 address inputs which select an 8-bit memory location during a read or write operation A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 A8 A8 A9 A9 A10 A10 A11 A11 A12 A12 I/O 0 I/O 0 data is written to or read from the PCF29F64 via the I/O pins I/O 1 I/O 1 I/O 2 I/O 2 I/O 3 I/O 3 I/O 4 I/O 4 I/O 5 I/O 5 I/O 6 I/O 6 I/O 7 I/O 7 negative supply voltage VSS negative supply voltage Chip Enable CE Chip Enable input which must be LOW to enable all read/write operations, when HIGH power consumption is reduced Output enable OE Output Enable input which controls the data output buffers and is used to initiate read operations not connected n.c. not connected Write enable WE Write Enable input which controls the writing of data to the PCF29F64 positive supply voltage VDD positive supply voltage Mode MODE selection of Erase mode is achieved by a HIGH at this input, LOW selects the Write mode Address bus address inputs which select an 8-bit memory location during a read or write operation 10 9 8 7 6 5 4 3 25 24 21 23 2 I/O Bus data is written to or read from the PCF29F64 via the I/O pins 11 12 13 15 16 17 18 19 Power 14 28 Control 1 20 22 27 Not connected 26 DC CHARACTERISTICS TIMING CHARACTERISTICS Read cycle Erase and Write cycle Limiting values DC CHARACTERISTICS Timing characteristics AC test conditions PCF29F64 8 K × 8-bit static CMOS EEPROM with PAGE-ERASE options 1.2 micron (n-channel floating gate) CMOS PCF29F64 P PCF29F64 T FEATURES

  • Low Power CMOS

  • maximum active current

  • maximum standby current

  • Access time

  • Fast Erase cycle time

  • 32-byte Erase operation (PAGE-Erase) 5 ms

  • 256-byte Erase operation (BLOCK-Erase) 5 ms

  • complete Memory Erase operation 5 ms

  • Fast Write cycle time

  • Data Polling allows user to minimize Write cycle time

  • Simple Write operation

  • single TTL-level WE signal

  • internally latched address and data

  • automatic Write timing

  • Endurance 10 000; Tamb=85 °C

  • 10 years non-volatile data retention time.

    •  GENERAL DESCRIPTION

    The PCF29F64 is an 8 K × 8-bit floating gate electrically erasable programmable read only memory (EEPROM), fabricated in a 1.2 micron n-chanel floating date CMOS technology.

    Power consumption is very low and reliability is high due to the full CMOS technology used, as that for the PCX8582 family.

    Three different Erase-operation modes are offered by the PCF29F64:

  • 32-byte Erase operation (PAGE)

  • 256-byte Erase operation (BLOCK)

  • Complete Memory Erase operation

    • A write operation is performed in approximately , which allows the entire memory to be written in less than 21 s.

    The PCF29F64 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs and EPROMs.

    Philips EPROMs and PAGE-EEPROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater that 10 years.

     QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT – – – – – – – – –
    ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE PCF29F64P 28 DIL plastic SOT117 PCF29F64T 28 SO28 plastic SOT136
     Block diagram. Pin Configuration. PINNING SYMBOL PIN DESCRIPTION to to , , , , , , to to , to
    LIMITING VALUES

    In accordance with Absolute Maximum Rating System (IEC 134).

    SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT – –
    <REFLECTION SOURCE.REF="PCIS758"></REFLECTION>

    = ; = ; = ; unless otherwise specified.

    SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies – = = ; = ; ; = ; = – – see Figs 4 to 7 – – = ; = ; = – – – – LOW level input voltage CMOS – TTL – HIGH level input voltage CMOS – TTL – = – – = – – = – – = ; = – – = – – = – – – –
    <REFLECTION SOURCE.REF="PCIS1373"></REFLECTION>

    = ; = ; unless otherwise specified.

    SYMBOL PARAMETER MIN. MAX. UNIT – – – – – – – – – – – – – – – – – – –
    AC TEST CONDITIONS
    Mode selection CE OE WE MODE I/O PIN POWER L L H read D OUT active L H L erase (MODE input = HIGH) - active L H L write (MODE input = LOW) D IN active H X X standby and E/W inhibit HIGH Z standby X L X E/W inhibit - X X H E/W inhibit -
    Erase Mode selection MODE/ADDRESS A0 to A2 A3 A4 A5 to A7 A8 to A12 PAGE X 0 0 valid valid BLOCK ERASE X 0 1 X valid (note 1) Note to Table 2

    If either A3 or A4 have a HIGH level, BLOCK ERASE mode is selected.

     BLOCK |ERASE X 1 0 X valid (note 1) FULL ERASE X 1 1 X X
    DEVICE OPERATIONS Read

    Read operations are initiated by both OE and CE set LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.

     Erase

    Erase operations are initiated when both CE and WE are LOW and OE and MODE are HIGH. The PCF29F64 supports a CE and WE controlled cycle. That is, the address is latched by the falling edge of either CE or WE, which ever occurs last.

    An erase operation, once initiated, will automatically continue to completion, typically within 5 ms.

     Write

    Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PCF29F64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 2.5 ms.

     <NOT>Data</NOT> Polling

    The PCF29F64 features Data polling as a method to indicate to the host system that the byte write cycle has completed. Data polling allows a simple bit test operation to determine the status of the PCF29F64 eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O 7

  • (i.e. write data = 0XXX XXXX; read data = 1XXX XXXX)

    • Once the programming cycle is complete, I/O 7 will reflect the true data.

         ERASE-WRITE PROTECTION

    There are three features that protect the non-volatile data from inadvertent Erase and Write operations.

  • Noise protection; write pulse of less that 20 ns will not initiate a write cycle.

  • VDD sense; all functions are inhibited when VDD is ≥ 3.5 V typically.

  • E/W inhibit; holding either OE LOW, WE HIGH or CE HIGH during power-on and power-off, will inhibit inadvertent Erase and Write operations.

    •  Timing Diagram; Read Cycle. Timing Diagram;<NOT>CE</NOT> controlled Erase cycle. Timing Diagram;<NOT>WE</NOT> controlled Erase cycle. Timing Diagram;<NOT>CE</NOT> controlled Write cycle. Timing Diagram;<NOT>WE</NOT> controlled Write cycle. Timing Diagram; <NOT>Data</NOT> polling. APPLICATION INFORMATION

    The use of Flash EEPROM (FEEPROM facilitates opportunities to make embedded applications where new releases of firmware or modified parameter sets can be programmed by means of in-circuit programming.

    Advantages of in-circuit programming over existing programming schemes are:

  • No loss of time due to UV erasing

  • No desoldering required. This is critical in applications with high component densities.

  • No expensive and large sockets required. This becomes important when e.g. QFP packages are used.

    • The in-circuit programming of FEEPROM in an application can be initiated via e.g. a terminal or PC. In-circuit programming may also be controlled from a remote location via e.g. an RS232, RS485 or a telephone link. This makes the modification of firmware in applications that are installed in remote locations (e.g. somewhere in an industrial factory) possible.

    The block diagram (Fig.9) gives an example of how to use the FEEPROM with an 80C51 family microcontroller for remote downloading of firmware and parameter sets via a telephone line. The system consists of an 80C51/87C51 microcontroller, a PCF29F64 8 k × 8 FEEPROM, an RS232 driver, a MODEM and some glue logic.

    The 80C51/87C51 contains firmware that has the following main tasks:

  • MODEM control and handshaking (e.g. RTS/CTS or XON/XOFF)

  • Protocol handling of downloaded file

  • Programming control of FEEPROM

    • The addresses of the FEEPROM are mapped in such a way, that they are greater than the highest memory address of the microcontroller. For an 80C51/87C51 this will be 4 K. To achieve this an external address decoder is used. The erase mode of the FEEPROM is controlled by the level on the MODE pin. This pin is connected to an address decoder output in such a way, that for erasing a shadow 8 K memory area exists. Erasing can be performed by a correct write action to this memory area.

    The CE signal for the FEEPROM is gated with the RESET of the microcontroller. The reason for this is to prevent unwanted write actions to the FEEPROM during power-up. This may occur when the power is already within the specified values, but the oscillator of the microcontroller has not yet started up. In this time frame the status of the microcontroller port pins is undefined.

    By combining the microcontroller RD and PSEN signals, the PCF29F64 is accessible as both program memory and external data memory.

    After power-on the program will start from the internal microcontroller program. This program will carry out some modem initialization and then jump to the user program in the PCF29F64. The interrupt vector addresses in the microcontroller must be remapped to the PCF29F64, so that execution of the user interrupt service routine is possible. When data is about to be received (via the RS232 DCD line or is received (UART interrupt), the download program in the microcontroller is started. The received data file should be an absolute output file such as e.g. an INTEL Intellec-8 HEX file. During the download/programming time, interrupts that are mapped to the PCF29F64 address space, should be disabled to prevent unintentional jumps to the FEEPROM. When the communication is finished and all data programmed in the FEEPROM, the firmware in the microcontroller may jump again to the user program in the PCF29F64.

    As previously mentioned, the PCF29F64 may be used as user program and external data memory. However, when the user program wants to program or erase FEEPROM location(s) in the same PCF29F64 device, program execution from this device is inhibited. A solution may be that the FEEPROM programming routines for the user program reside in the microcontroller program memory. Program execution should stay there in a loop, until programming or erasing of the PCF29F64 is finished. Remapped interrupts to a PCF29f64 device that will be programmed, should be disabled to prevent unintentional jumps to this device. When program execution is carried out from the internal microcontroller memory, the AD0 to AD7 pins will float. To assure defined levels on the I/O0 to I/O7 pins of the FEEPROM, pull-up resistors.

    Application diagram     PACKAGE OUTLINES 28-lead dual in-line; plastic (SOT117). 28-lead mini-pack; plastic (SO28; SOT136). SOLDERING Plastic dual in-line packages By dip or wave

    The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s.

    The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

     Repairing soldered joints

    Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s.

         SOLDERING Plastic mini-packs By wave

    During placement and before soldering, the component must be fixed with a droplet of adhesive. After cutting the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing.

    Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C.

    A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications.

     By solder paste reflow

    Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stenciling or pressure-syringe dispensing before device placement.

    Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C.

    Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C.

     Repairing soldered joints (by hand-held soldering iron or pulse-heated solder tool)

    Fix the components by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.

    For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.

         DEFINITIONS DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values

    Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may effect device reliability.

     Application Information

    Where application information is given, it is advisory and does not form part of the specification.

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    ℗Philips Electronics N.V. 1993

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